designing a fast locking pll

a phase-locked loop (pll) based frequency synthesizer is an important circuit that is used in many applications, especially in communication systems such as ethernet receivers, disk drive read/write channels, digital mobile receivers, high-speed memory interfaces, system clock recovery and wireless communication system. other than requiring good signal purity such as low phase noise and low spurs from the frequency synthesizers, locking speed is an important design requirement. fast-locking capability is particularly critical for systems demanding frequency working operation. a phase-locked loop (pll) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator. the main blocks of the pll are the phase frequency detector (pfd), charge pump, loop filter, voltage controlled oscillator (vco), and counters, such as a feedback counter (m), a pre-scale counter (n), and post-scale counters(c). plls align the rising edge of the reference input clock to a feedback clock using the pfd. the falling edges are determined by the duty-cycle specified by the user. the pfd detects the difference in phase and frequency between the reference clock and feedback clock inputs and generates an ?up? or ?down? control signal based on whether the feedback frequency is lagging or leading the reference frequency. these ?up? or ?down? control signals determine whether the vco needs to operate at a higher or lower frequency, respectively. this paper presents a fast-locking technique for phase-locked loops (plls). in this proposed technique, the polarity and magnitude of the phase error at two phase-frequency detectors (pfd) input is continuously monitored during the locking process. first pfd detects the difference between rising edge of reference signal and output signal. second pfd detects the difference between falling edge of reference signal and output signal. the detected phase and frequency error is then coarsely compensated by a proper voltage for voltage control oscillator (vco), that is produced by a programmable charge pump (cp). the proposed method compensates phase and frequency error together and at the same time.